An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology

After the LHC luminosity upgrade the number of readout channels in the ATLAS Inner Detector will be increased by one order of magnitude and delivering the power to the front-end electronics as well as cooling will become a critical system issue. Therefore a new solution for powering the readout electronics has to be worked out. Two main approaches for the power distribution are under development, the serial powering of a chain of modules and the parallel powering with a DCDC conversion stage on the detector. In both cases switchedcapacitor converters in the CMOS front-end chips will be used. In the paper we present the design study of a step-up charge pump and a step-down converter. In optimized designs power efficiency of 85 % for the step-up converter and 92 % for the step-down converter has been achieved

High-rate GPS positioning for tracing anthropogenic seismic activity. The 29 January 2019 mining tremor in Legnica- Głogów Copper District, Poland

High-rate GNSS observations are usually studied in relation to earthquake analysis and structural monitoring. Most of the previous research on short-term dynamic deformations has been limited to natural earthquakes with magnitudes exceeding 5 and amplitudes equal to several dozen centimetres. High-frequency position monitoring via GNSS stations is particularly important in mining areas due to the need to monitor mining damages. On 29 January 2019 (12:53:44 UTC), an M3.7 event occurred in the area of Legnica-Głogów Copper District. This study presents GPS-derived displacement analysis in relation to seismological data. Station position time series were determined by double differencing and Precise Point Positioning. The peak ground displacement was 2–14 mm. The correlation coefficients between GPS and seismological displacement time series reached 0.92. A statistical evaluation of GPS displacement time series was carried out to detect an event using only GPS observations

VFAT2: A front-end system on chip providing fast trigger information, digitized data storage and formatting for the charge sensitive readout of multi-channel silicon and gas particle detectors

The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger building outputs, digital data tagging and storage, data formatting and data packet transmission with error protection. VFAT2 is designed to work in the demanding radiation environments posed by modern H.E.P. experiments and in particular the TOTEM experiment of the LHC. Measured results are presented demonstrating full functionality and excellent analog performance despite intensive digital activity on the same piece of silicon

Підготовка адвокатом позовної заяви до суду

Аналізуються питання, пов’язані із підготовкою адвокатом позовної заяви до суду.Анализируется вопросы связаны с подготовкой адвокатом искового заявления в суд.The question connected with preparation of the point of claim to the court by the lawyer is analysed

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade

We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25 μm technology and optimised for the short, 2.5 cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We have obtained the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in view of the minimization of the power consumption, as the upgrade detector may contain up to 70 million of channels. System tests with different power distribution schemes proposed for the future tracker detectors are possible with this chip. The ABCN-25 ASIC is now serving as the prototype readout chip in the developments of the modules and staves for the upgrade of the ATLAS Inner Detector